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STV5342 teletext decoder with 4 integrated pages april 1994 . complete teletext decoder includ- ing on-chip 4 pages memory, reduc- ing emc radiations . upward software and hardware compatible with previous sgs-thom- son's decoder sda5243 . automatic selection of up to six na- tional languages . 4 simultaneous page requests . display of the 25th status row . microprocessor control via an i 2 c bus (slave address 0010001 r/w) . data acquisition available from lines 2 to 22 or from a complete field . high quality display using a charac- ter matrix of 12 x 10 dots . single + 5v supply voltage . on-chip mask programmable rom character generators . hcmos process 1 2 3 4 5 6 7 8 9 10 11 12 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 24 23 22 21 ttd ttc odd/even f6 sand tcs/scs r g b cor bl an y scl sda v dd v ss vcs reserved reserved 5342-01.eps pin connections description the STV5342 is a hcmos integrated circuit which performs all the processing of logical data within a 625 lines system teletext decoder. it is designed to operate in conjunction with one-chip : the saa5231 integrated chip which extracts teletext information embedded in a composite video signal. up to 4 pages of display data can be stored in internal memory. a complete system also comprises a mi- croprocessor controlling the STV5342 via a 2-wires serial bus. an on-chip rom memory contains the character sets. the STV5342 performs automatic selection of one of up to six natural languages. data bytes may be decoded in either 7-bit plus parity or in full 8-bit formats. the chip set also supports facilities for reception and display of higher-level protocol data. dip40 (plastic package) order code : STV5342 1/20
pin description pin symbol function description 1v dd +5v positive supply voltage 2to5 22 to 40 reserved not used 6 ttd teletext data input an a.c. coupled teletext data input supplied by the saa5231 chip is latched to v ss between 4 and 8 m s after each tv line. 7 ttc teletext clock input a 6.9375mhz clock signal, supplied by the saa5231 chip, is internally a.c. coupled, clamped and buffered. 8 odd/even interlaced mode state output high for even numbered and low for odd numbered frames. the value is valid 2 m s before the end of lines 311 and 624. 9 f6 character display clock signal the 6mhz clock signal, supplied by the saa5231 chip is internally a.c. coupled, clamped and buffered. 10 vcs video composite synchronization input signal active high vcs input. 11 sand sandcastle three level output pulse to the saa5231 device. phase lock, blanking signal, and color burst components are contained in this signal. 12 tcs/scs input / output composite synchronization signal scan composite input signal (scs) for the display synchronization or text composite sync. (tcs) output signal to the saa5231. both signals are active low. 13,14,15 r g b red, green, blue character and background colors active-high open-drain outputs. 16 cor contrast reduction open-drain active-low output supporting optimal display of characters in omixed modeo operation. 17 blan blanking signal output open-drain active high output for tv-image blanking in normal and mixed-mode operation. 18 y foreground output open-drain active-high output with foreground information. can be used for printer command. 19 scl serial clock microprocessor clock input via serial bus. 20 sda serial data input / output open-drain microprocessor serial data input/output via serial bus. 21 v ss 0 volt ground 5342-01.tbl STV5342 2/20
data address ctrl address ctrl data data cloc k red green blue scl sda ttc ttd f6 vcs sand tcs/ scs v dd v ss yblan cor odd/ even pins 22 to 40 and pins 2 to 5 not used 4 pages internal memory external memory interface time base data acquisition & data processing display & control interface i c bus interface 2 9 7 6 19 20 121 1817168 15 14 13 10 11 12 5342-02.eps block diagram absolute maximum ratings symbol parameter value unit v dd power supply range -0.3, +6.0 v input voltage range : v i vcs,sda,scl,d0-d7 -0.3, v dd + 0.5 v v i ttd,f6,tcs/scs,tt c -0.3, +10 v output voltage range : v o sand,sda,odd/even,r,g,b -0.3 , v dd v v o blan,cor, y, tcs/scs -0.3 , v dd v t stg storage temperature range -20, +125 o c t a operating ambient temperature range -20, +70 o c 5342-02.tbl electrical characteristics v dd = 5v, v ss = 0v, t a = - 20 to + 70 o c symbol parameter min typ max unit v dd supply voltage (pin 1) 4.5 5 5.5 v i dd supply current (operating mode) 15 40 ma 5342-03.tbl STV5342 3/20
electrical characteristics (continued) v dd = 5v, v ss = 0v, t a = - 20 to + 70 o c symbol parameter min typ max unit inputs ttd (pin 6) c ext ext. coupling capacitor 50 nf v i(p-p) input voltage p-p 2 7 v t r ,t f input rise / fall times 10 80 ns t ds input set-up time 40 ns t dh input hold time 40 ns i i(l) input leakage current (v i = 0 to v dd ) -10 +10 m a c i input capacitance 7pf ttc, f6 (pins 7,9) v i dc input voltage - 0.3 +10 v v i(p-p) ac input voltage f6 ac input voltage ttc 1 1.5 7 7 v v v p input peak rel. 50 % duty 0.2 3.5 v f ttc ttc clock frequency 6.9375 mhz f f6 f6 clock frequency 6 mhz t r ,t f clock rise / fall times 10 80 ns i i(l) input leakage current (v i = 0 to 10v) -10 +10 m a c i input capacitance 10 pf vcs (pin 10) v il low level input voltage 0 0.8 v v ih high level input voltage 2 v dd v t r ,t f input rise / fall times 500 ns i i(l) input leakage current (v i = 0 to v dd ) -10 +10 m a c i input capacitance 7pf scl (pin 19) v il low level input voltage 0 1.5 v v ih high level input voltage 3 v dd v f scl scl clock frequency 100 khz t r ,t f input rise / fall times 2 m s i i(l) input leakage current (v i = 0 to v dd ) -10 +10 m a c i input capacitance 7pf input/outputs tcs(output), scs(input) (pin12) v il low level input voltage 0 1.5 v v ih high level input voltage 3 8 v t r ,t f input rise / fall times 500 ns i i(l) input leakage current (v i = 0 to v dd and output in high impedance state) -10 +10 m a c i input capacitance 7pf v ol low level output voltage (i ol = 0.4ma) 0 0.4 v v oh high level output voltage (-i oh = 0.2ma) 2.4 v dd v t r ,t f output rise / fall times between 0.6v and 2.2v 100 ns c l load capacitance 50 pf 5342-04.tbl STV5342 4/20
electrical characteristics (continued) v dd = 5v, v ss = 0v, t a = - 20 to + 70 o c symbol parameter min typ max unit input/outputs (continued) sda (pin 20) v il low level input voltage 0 1.5 v v ih high level input voltage 3 v dd v t r, t f input rise / fall times 2 m s i i(l) input leakage current (v i = 0 to v dd and output in high impedance state) -10 +10 m a c i input capacitance 7pf v ol low level output voltage (i ol = 3ma) 0 0.5 v t f output fall time between 3.0v and 1.0v 200 ns c l load capacitance 400 pf d0-d7 (pins 22-29) v il low level input voltage 0 0.8 v v ih high level input voltage 2 v dd v i i(l) input leakage current (v i = 0 to v dd and output in high impedance state) -10 +10 m a c i input capacitance 7pf v ol low level output voltage (i ol = 1.6ma) 0 0.4 v v oh high level output voltage (-i oh = 0.2ma) 2.4 v dd v t r, t f output rise / fall times between 0.6v and 2.2v 50 ns c l load capacitance 120 pf outputs odd/even ?? (pin 8) v ol low level output voltage (i ol = 0.4ma) 0 0.4 v v oh high level output voltage (-i oh = 0.2ma) 2.4 v dd v t r ,t f output rise / fall times between 0.6v and 2.2v 100 ns c l load capacitance 50 pf sand (pin 11) v ol low level output voltage (i ol = 0.2ma) 0 - 0.25 v v oi middle level output voltage (i ol = 10 m a) 1.1 - 2.9 v v oh high level output voltage (-i oh = 0 to 10 m a) 4v dd v t r1 t r2 output rise time : v ol to v oi from 0.4 to 1.1v v oi to v oh from 2.9 to 4.0v - - - - 400 200 ns t f output fall time v oh to v ol from 4.0 to 0.4v - - 50 ns c l load capacitance - - 30 pf r, g, b, cor, blan, y (pins 13-18) v ol low level output voltage : i ol = 2ma i ol = 5ma 0 0 - - 0.4 1 v v pu pull-up voltage (with r = 1k w to v dd ) --v dd v t f output fall time from 4.5 to 1.5v (with r = 1k w to v dd ) - - 20 ns t sk skew delay on falling edges (at 3v with r = 1k w connected to v dd ) - - 20 ns c l load capacitance - - 25 pf i lo output leakage current (v pu = 0 to v dd output off) - - 20 m a 5342-05.tbl STV5342 5/20
electrical characteristics (continued) v dd = 5v, v ss = 0v, t a = - 20 to + 70 o c symbol parameter min typ max unit timing serial bus (referred to v ih =3v,v il = 1.5v) (see fig. 6) t low low period clock 4 - - m s t high high period clock 4 - - m s t su , dat data set-up time 250 - - ns t hd , dat data hold time 170 - - ns t su ,s to stop set-up time from clock high 4 - - m s t buf start set-up time following a stop 4 - - m s t hd , sta start hold time 4 - - m s t su , sta start set-up time following clock low to high transition 4 - - m s 5342-06.tbl 6 9 7 character display clock input to timing chain teletext clock input to data acquistion circuit teletext data input to data acquisition circuit clamping pulses from timing circuit from time 4 m sto8 m s of each television line to maintain correct d.c. level following external a.c. coupling f6, ttc, ttd input circuitry input waveform parameters shaded regions equal in area v 0t 50% duty cycle level v p v i(p-p) v p f6 ttc ttd c ext 5342-03.eps figure 1 : f6, ttc, ttd input internal connections 144ns typ. t cy 40ns min. 40ns min. t dh t ds 80ns max. t r t f 80ns max. 10% 90% 90% 10% data stable data stable data may change data may change data may change ttc ttd 5342-04.eps data stable : 1 if 2v , 0 if 0.8v figure 2 : teletext data input timing STV5342 6/20
f1 tcs sand 0 4.67 8.5 1.5 33.5 64 continuous internal 1mhz clock phase lock off all timings in m s phase lock 5342-05.eps figure 3 : synchronization timing lsp ep bp tcs (interlaced) tcs (interlaced) tcs (non-interlaced) 0 0 0 2.33 4.66 32 34.33 32 27.33 59.33 64 64 64 all timings in m s 621 (308) 622 (309) 623 (310) 624 (311) 625 (312) 12 3456 309 310 311 312 313 314 (1) 315 (2) 316 (3) 317 (4) 318 (5) 319 (6) 308 309 310 311 312 1 2 3 4 5 6 the number positions indicate the end of lines. the teletext composite synchronization signal (tcs), whether interlacing is present or not, comprise three components. a) the line-synchronization pulses (lsp). b) the equalization pulses (ep) c) the frame-synchronization pulses (bp). the timing reference is specified by the descending edge of the signal lsp, with a tolerance spread of 100ns. 5342-06.eps figure 4 : composite sync. waveforms STV5342 7/20
0 4.66 0 16.67 64 56.67 312 291 41 0 40 m s display period lines 42 to 291 inclusive (and 355 to 604 inclusive interlaced) display period lsp (tcs) r.g.b.y (1) r.g.b.y (1) a) line rate b) field rate all timings in m s line numbers (1) also blan in charac ter and box bla nking horizontal directio n(line ) - vertical direc tion (frame) 5342-07.eps figure 5 : display output timing t buf t low t high t f t r t hd,sta t hd,dat t su,dat t su,sta t su,sto sda scl sda 5342-08.eps v ih =3v,v il = 1.5v figure 6 : serial bus timing STV5342 8/20
6mhz oscillator phase detector signal quality detector tcs outputs buffer 9 11 10 12 17 22 25 28 1 27 6mhz 15.625khz f6 sand vcs tcs/scs cvbs tcs 6 64 teletext data and clock separator switch in this position tcs on v s or 1.2k w 70 m a enable tcs on (d2 = 1) mode (d1/d0) i c-register 1 2 saa5231 data slicer STV5342 videotext controller sensor pin 28 voltage video scan composite sync. sync. vertical integrator sync. composite sync. generator line sync enable acquisition system clock acquisition field sync. display field sync. sync. output composite sync. separator 5342-09.eps figure 7 : master synchronization mode STV5342 9/20
6mhz oscillator videotext data and clock separator phase detector signal quality detector tcs outputs buffer 9 11 10 12 17 22 25 28 1 27 18 20 6mhz 15.625khz f6 sand vcs tcs/scs disable not connected for external synchronization c l cvbs tcs 664 2 scs (d1=d0=1) (d2=0) ext-sync i c - register 1, bit d2=0 to disable tcs output buffer and d1=d0=1 to enable external sync. acquisition only works when external sync. signal is phase synchronous with cbvs input. tcs off determines f6 and line sync. sync. separator sync. integrator composite sync. generator scs field sync. internal clock enable acquisition display field sync. field sync. line sync. data slicer saa5231 STV5342 videotext controller i c-register 1 2 composite scan sync. video sync. composite 5342-10.eps figure 8 : slave synchronization mode STV5342 10/20
15 28 22 17 25 2 3 4 5 6 9 24 26 13 6 12 7 16 18 11 9 10 14 19 21 8 220pf 68nf 100pf 270pf 22nf 1nf 15pf 47nf 47nf 470pf 10nf 47nf 560pf saa5231 19 20 1 21 +5v 16 1 10 7 11 18 20 23 12 15pf 13.875mhz 6mhz 7-36 27pf 10pf +12v 82 3 76 1 tea2014a 5 27 17 13 14 15 21 3 v 0 v 1 gnd +5v 150pf +12v l7805 +12v blk g b gnd r sync video +12v gnd scl sda t s 10k w 470 w 470 w 10k w 1k w 4.7 m f15 m h 68k w 390 w 10k w 820 w 10 w 10 m f 470 w 1k w 1k w 2.2 m f 10 m f 47 m f +12v bc558b 22 m h 0.1 m f 22 m h 23nf 8 STV5342 1n4148 bc548b bc548b bc548b bc548b 82 w 82 w 82 w 82 w 2.7k w 1k w 1k w 1k w 22 m f 100 w 6.8k w 1.2k w 4.7k w 3.7k w 5342-11.eps application diagram STV5342 11/20
1 7248 10 14 this row always free for status 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 row 8 scrolling time characters 24 characters from page header rolling on page search fixed characters alphanumerics white for normal, green on searc h 7 status characters main page display area 14 bytes free for use by m c 10 bytes for received page information 5342-12.eps page memory organization figure 9 application notes organization of a page-memory the organization of a page-memory is shown in figure 9. the STV5342 chip provides a display format of 25 rows of 40 characters per row. row number twenty-four is used by the microproc- essor for the display of information. row zero contains the page header. the organization is as follows : the first seven characters (0 - 6) are used for messages regarding the operational status. the eighth character is an alphanumeric control character either owhiteo or ogreeno defining the osearcho status of the page. when it is owhiteo the operational state is normal and the header appears white ; when it is ogreeno the operational state corresponds to osearch modeo and the header appears green. the following twenty-four charac- ters give the header of the requested page when the system is in search mode. the last eight char- acters display the time of day. row twenty-five comprises ten bytes of control data concerning the received page (see table 1) and fourteen free bytes which can be used by the microprocessor. STV5342 12/20
d0 pu0 pt0 mu0 mt0 hu0 ht0 c7 c11 mag0 0 d1 pu1 pt1 mu1 mt1 hu1 ht1 c8 c12 mag1 0 d2 pu2 pt2 mu2 mt2 hu2 c5 c9 c13 mag2 0 d3 pu3 pt3 mu3 c4 hu3 c6 c10 c14 0 0 d4 ham ham ham ham ham ham ham ham found 0 d5 000000000 pblf d6 0000000000 d7 0000000000 column 0123456789 page number : - mag = magazine, pu = page units, pt = page tens. page sub-code : - mu = minutes units, mt = minutes tens, hu = hours units, ht = hours tens. pblf = page being looked for, found = low for page found, ham = hamming error in byte, c4-14 = control bits. 5342-08.tbl table 1 : row 25 received page control data format 8/30 reading 8/30 packet is read at row 23 equivalent address. r8 register must be programmed with d3, d2, d0 = 0 and d2 = 1 (8/30 selection). r9 register must be programmed with 23 (17h). r10 register value corresponds to the position of the byte to be read (from 0 to 39). r11a contents the value of the needed byte. d7 d6 d5 d4 d3 d2 d1 d0 * * * * * even off tc sel11b r0 mode 0 ta 7 + p/ 8 bit acq. on/off 8/30 enable dew/ full field tcs on t1 t0 r1 mode 1 * * acq cct a1 acq. cct a0 tb start column sc2 start column sc1 start column sc0 r2 page request adress * * * prd4 prd3 prd2 prd1 prd0 r3 page request data * * * * **a1a0 r4 display chapter bkgnd out bkgnd in cor out cor in text out text in pon out pon in r5 display control (normal) bkgnd out bkgnd in cor out cor in text out text in pon out pon in r6 display control (newsflash / subtitle) status row btm/top cursor on conceal/ reveal top/ bottom single/ double height box on 24 box on 1-23 box on 0 r7 display mode * * * * clear mem. 8/30 select a1 a0 r8 active chapter * * * r4 r3r2r1r0 r9 active row * * c5 c4 c3 c2 c1 c0 r10 active column d7 (r/w) d6 (r/w) d5 (r/w) d4 (r/w) d3 (r/w) d2 (r/w) d1 (r/w) d0 (r/w) r11a active data 60hz 0 0 0 0 0 0 vcs signal quality r11b status * reserved register bits : must be set to 0 ? ? ? ? ? ? ? ? 5342-09.tbl table 2 : register specification register map (see table 2) registers r0 to r10 are write only whilst r11a is a read/write and r11b is a read only register respect to the microprocessor. the automatic succession on a byte basis is indi- cated by the arrows in table 2. in the normal operating mode ta, tb and tc should be set to logic level 0. after power-up the contents of the registers are as follows : all bits in registers r0 to r11a are cleared to zero with the exception of bits d0 and d1 in registers r5 and r6 which are set to logical one. after power-up all the memory bytes are preset to hexadecimalvalue 20 h (space) with the exception of the byte corresponding to row 0 of column 7 of chapter 0 which is set to the value corresponding to oalpha whiteo hexadecimal value 07 h. STV5342 13/20
register functions register function bit(s) description r0 address 00h r11 adressing and pin functions control sel 11b (d0) selection of register 11b (d0 = 1) or 11a (d0 = 0) tc (d1) test bit, must be cleared in the normal working mode even off (d2) control of odd/even pin : even signal output (d2 = 0) or grounded (d2 = 1) r1 address 01h operating mode controls t1 t0 00 01 10 11 312/313 line mix - mode with interlace 312/313 line text - mode without interlace 312/312 line terminal mode without interlace external synchronization tcs/scs is an input tcs on (d2) d2 = 1, tcs output on pin tcs/scs d2 = 0, scs input on pin tcs/scs dew / fullfield (d3) selection of field flyback mode or full channel mode (d3 = 1) 8/30 enable (d4) selection of 8/30 packet acquisition (d4 = 1) acquisition on / off (d5) control of acquisition operation (d5 = 0 enables acquisition) 7 bits + parity or 8 bits without parity (d6) selection of received data format either 7 bits with parity (d6 = 0) or 8 bits without parity (d6 = 1). ta (d7) test bit, must be cleared in the normal working mode r2 address 02h addressing information for a page request sc0, sc1, sc2 (d0, d1, d2) address the first column of the on chip page request ram to be written. tb (d3) test bit, must be cleared in the normal working mode. a0 - d4 a1 - d5 selection of acquisition circuit (1 of 4) r3 address 03h data relative to the requested page (see table 3) prd0 - prd4 (d0 - d4) written data in the page request ram, starting with the columns addressed by sc0,sc1,sc2. r4 address 04h selection of one of 4 pages to display a0 - d0 a1 - d1 selection of page to be displayed r5 address 05h display control for normal operation pon (d0, d1) picture on (in: d0, out: d1) text (d2, d3) text on (in: d2, out: d3) cor (d4, d5) contrast reduction on (in: d4, out: d5) bkgnd (d6, d7) background colour on (in: d6, out: d7) in / out enable inside/outside the box r6 address 06h display control for news-flash subtitle generation see r5 see r5 r7 address 07h display mode box on 0, 1-23,24 (d0, d1, d2) the oboxingo function is enabled on row 0,1-23 and 24 by d0, d1 and d2 set to one. top/bottom single/double height (d4/d3) x0 = normal 01 = double height rows 0 to 11 11 = double height rows 12 to 23 conceal/reveal (d5) conceal reveal function cursor on/off (d6) cursor position given by row/column value of r9/r10 status row btm / top (d7) the 25th row is displayed before the omain text areao (lines 0-23) or after (d7 = 0). r8 address 08h active chapter address a0 (d0) a1 (d1) selection of chapter to be read/write 8/30 select(d2) to read 8/30 packet r8, d0 and d1 must be o0o and d2 = 1 5342-10.tbl STV5342 14/20
register functions register function bit(s) description r9 to r11a address 09h to 0bh* active row address (r9), active column address (r10). data contained in r11a read (written) from (to) memory by microprocessor via i 2 c. r11b address 0bh* status vcs signal quality (d0) good vcs quality signal detected (d0 = 1) or disturbed (d0 = 0) 60hz (d7) vcs received with 60hz frequency (d7 = 1) or 50hz (d7 = 0). only valid when vcs is good (d0 = 1) * reading of r11a or r11b is determined by register 0, bit d0. nevertheless, write operation is always performed on r11a register. 5342-11.tbl start column prd4 prd3 prd2 prd1 prd0 0 do care magazine hold mag2 mag1 mag0 1 do care page tens pt3 pt2 pt1 pt0 2 do care page units pu3 pu2 pu1 pu0 3 do care hours tens x x ht1 ht0 4 do care hours units hu3 hu2 hu1 hu0 5 do care minutes tens x mt2 mt1 mt0 6 do care minutes units mu3 mu2 mu1 mu0 the abbreviations have the same significance as in table 1 with the exception of the odo careo entries. it is only when this bit is o1o that the corresponding digit is taken into consideration on page request. for example, a page defined as onormalo or one defined as otimedo may be selected. if oholdo is low the page is held. the addressing of successive bytes via the i 2 c bus is automatic. 5342-12.tbl table 3 : register r3 character sets the complete character set with 8-bit decoding is given in table 4. characters in columns 0 and 1 are normally dis- played as blanks. black dots represent the charac- ter shape whereas white dots represent the background. each character can be identified by a pair of corre- sponding row and column integers : for example the character o3o may be indicated by 3/3. a rectangle may be represented as follows : the characters 8/6, 8/7, 9/5, 9/7 are used as spe- cial characters, always in conjunction with 8/5. the 13 national characters are placed in columns with bit 8 = 0. STV5342 15/20
22a 0 1 0 or 1 0 0 1 0 0 b 8 b 7 b 6 b 5 b 4 b 3 b 2 b 1 b i t s column r o w 33a4 5 66a77a8 912131415 0 0 1 0 0 0 1 0 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 0 1 1 0 1 1 0 1 or 1 0 1 0 0 0 0 0 0 1 2 0000 1 000 0010 0011 0100 0101 0111 1000 1001 1010 1011 1100 1101 1110 1111 0 1 2 3 4 5 6 0110 7 8 9 10 11 12 13 14 15 alphanumerics red alphanumerics green alphanumerics black alphanumerics yellow alphanumerics blue alphanumerics magenta alphanumerics cyan alphanumerics white ** flash ** ** steady end box ** start box normal height double height * * so si ** release graphics hold graphics new background ** * esc separated graphics ** continuous graphics conceal display black background ** graphics white graphics cyan graphics magenta graphics blue graphics yellow graphics green graphics red graphics black case using c12 c13 c14 = 001 (german set) * these control characters are reserved for compatibility with other data codes. ** these control characters are presumed before each row begins 5342-13.eps table 4 : complete character set (with 8 bit codes) - west european languages STV5342 16/20
2/0 2/1 2/2 2/3 2/4 2/5 2/6 2/7 2/8 2/9 2/10 2/11 2/12 2/13 2/14 2/15 3/0 3/1 3/2 3/3 3/4 3/5 3/6 3/7 3/8 3/9 3/10 3/11 3/12 3/13 3/14 3/15 4/0 4/1 4/2 4/3 4/4 4/5 4/6 4/7 4/9 4/8 4/10 4/11 4/12 4/13 4/14 4/15 5/0 5/1 5/2 5/3 5/4 5/5 5/6 5/7 5/8 5/9 5/10 5/11 5/12 5/13 5/14 5/15 6/0 6/1 6/2 6/3 6/4 6/5 6/6 6/7 6/8 6/9 6/10 6/11 6/12 6/13 6/14 6/15 7/0 7/1 7/2 7/3 7/4 7/5 7/6 7/7 7/8 7/9 7/10 7/11 7/12 7/13 7/14 7/15 national character national character national character national character national character national character national character national character national character national character national character national character national character 5342-14.eps table 5 : basic character set. national option character sets the basic set of the 96 characters is shown in table 5.the location of the 13 national characters are shown in table 5 whilst full national character sets are depicted in table 6. STV5342 17/20
language english german swedish italian french spanish c12 c13 c14 phcb (1) 000 001 00 1 011 100 101 2/3 2/4 4/0 5/11 5/12 5/13 5/14 5/15 6/0 7/11 7/12 7/13 7/14 character position (column/row) 5342-15.eps table 6 : character set for STV5342 west european languages note 1 : where phcb are the page header control bits. other combinations de fault to english. only the above ch aracters change with the phcb. all others characters in the basic set are shown in table 5. STV5342 18/20
alphanumerics and graphics 'space' character 2/0 alphanumerics character 2/13 alphanumerics or blast-thro ugh alphanumerics character 4/8 alphanumerics character 7/15 contiguous graphics character 7/15 separated graphics character 7/15 separated graphics character 7/6 contiguous graphics character 7/6 background color display color = = 5342-16.eps figure 10 : character format STV5342 19/20
40 i a1 l b2 e d e3 f b1 e 21 120 b pm-dip40.eps package mechanical data 40 pins - plastic dip dimensions millimeters inches min. typ. max. min. typ. max. a1 0.63 0.025 b 0.45 0.018 b1 0.23 0.31 0.009 0.012 b2 1.27 0.050 d 52.58 2.070 e 15.2 16.68 0.598 0.657 e 2.54 0.100 e3 48.26 1.900 f 14.1 0.555 i 4.445 0.175 l 3.3 0.130 dip40.tbl information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no licence is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specifications mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of sgs-thomson microelectronics. ? 1994 sgs-thomson microelectronics - all rights reserved purchase of i 2 c components of sgs-thomson microelectronics, conveys a license under the philips i 2 c patent. rights to use these components in a i 2 c system, is granted provided that the system conforms to the i 2 c standard specifications as defined by philips. sgs-thomson microelectronics group of companies australia - brazil - china - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco the netherlands - singapore - spain - sweden - switzerland - taiwan - thailand - united kingdom - u.s.a. STV5342 20/20

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